Frequency synthesizers have traditionally made use of loop dividers which are designed to operate on an output frequency signal of a voltage controlled oscillator (VCO). Integer frequency synthesizers generally use loop dividers which divide an input frequency to a lower output frequency using a complete input frequency cycle period, or two pi (2.pi.) radians, as the minimum unit of resolution. Fractional frequency synthesizers also employ frequency loop dividers which use 2.pi. radians as the minimum unit of resolution. Typically, the loop dividers used in fractional frequency synthesizers obtain a fractional frequency divide value by periodically changing the integer value of loop divider so that, over several cycles of the output waveform, the average divide includes a fractional component. While the method of averaging a loop divider value does produce an output signal at the desired divided down frequency, lower frequency subharmonics are also present in the output. The subharmonic frequency components are not desirable in frequency synthesizers since they introduce unwanted noise energy in the output spectrum. Often, the subharmonic frequency components must be attenuated by low pass filtering within the frequency synthesizer, which consequently increases the lock time, and decreases VCO sideband noise attenuation. The practice of dividing, and fractionalizing a divided value in units of complete input clock cycles results in low frequency, and relatively large amplitude subharmonic spurs, which require such filtering. It would be beneficial to develop a method by which a fractional frequency synthesizer would produce subharmonic spurs that occur at higher frequencies and at smaller amplitudes. This would reduce filtering requirements and improve synthesizer performance.